Cadence Design Systems has released the Cadence Integrity 3D-IC platform, claimed to be the industry’s first comprehensive, high-capacity 3D-IC platform that combines 3D design planning, implementation, and system analysis in a single, unified cockpit. The platform underpins the company’s third-generation 3D-IC solution, providing customers with system-driven power, performance, and area for individual chiplets through integrated thermal, power and static timing analysis capabilities.
Chip designers creating hyperscale computing, consumer, 5G communications, mobile and automotive applications can deliver greater productivity with the platform versus a disjointed die-by-die implementation approach. The platform uniquely offers system planning, integrated electrothermal, static timing analysis, and physical verification flows, facilitating faster, high-quality 3D design closure. It also includes 3D exploration flows, which take 2D design netlists to produce multiple 3D stacking scenarios based on user input, automatically picking the optimal, final 3D stacked configuration. Furthermore, the platform database supports all 3D design types, allowing engineers to create designs at multiple process nodes simultaneously and achieve seamless co-design with package design teams and outsourced Semiconductor assembly and test companies that use Cadence Allegro packaging technologies.
“Cadence has historically offered customers strong 3D-IC packaging solutions through its leading digital, analog and package implementation product lines,” said Dr Chin-Chi Teng, senior vice president and general manager in the Digital and Signoff Group at Cadence. “With recent developments in advanced packaging technologies, we saw a need to further build upon our successful 3D-IC foundation, providing a more tightly integrated platform that ties our implementation technology with system-level planning and analysis. As the industry continues to move toward different configurations of 3D stacked dies, the new Integrity 3D-IC platform lets customers achieve system-driven PPA, reduced design complexity and faster time to market.”