Aldec provides easier access to FPGA-based ASIC & SoC prototyping

Aldec provides easier access to FPGA-based ASIC & SoC prototyping

Aldec provides easier access to FPGA-based ASIC & SoC prototyping

Aldec has launched the HES-DVM Proto ‘Cloud Edition’, giving engineers easier access to FPGA-based ASIC and SoC prototyping.

Available through Amazon Web Service (AWS), the HES-DVM Proto CE can be used for FPGA-based prototyping of SoC/ASIC designs and has a focus on automated design partitioning to reduce bring-up time when up to four FPGAs are needed to accommodate a design.

HES-DVM Proto CE can be used with Aldec’s HES pre-silicon prototyping boards, third party boards or platforms users may have developed in-house, so it can be used on projects with short prototyping phases. Alternatively, for companies working on multiple projects, HES-DVM Proto CE is able to evaluate HES-DVM before committing to investing in the traditional licensed version.

According to Zibi Zalewski, General Manager of Aldec’s Hardware Division, current SoCs are designed to meet many ASIC type requirements, such as power efficiency, clock distribution, gating and hierarchical bus architecture to assure the highest performance, avoid deadlocks and minimize power demand peaks.

“Meeting these many ASIC requirements calls for a design architecture and hierarchy that rarely fits easily into an FPGA-based prototyping platform because of the way resources need to be allocated and interconnections made,” he explained. “Changing the design hierarchy for the sake of the prototyping stage is to be avoided, so it is important to have a tool which will automatically create balanced partitions – picking and placing module instances across the original design hierarchy. The tool should also provide a fine grade of controllability and advanced analysis for timing critical paths or evaluating alternative FPGA partitioning schemes and their impact on interconnections.”

Of equal importance, explained Zalewski, is the automatic handling of I/O connections with LVDS-based serializers to resolve issues caused by limited numbers of FPGA I/Os.

HES-DVM Proto CE is delivered as an AWS AMI ready-to-use environment with DVM partitioning software and Aldec’s SyntHESer fast synthesis engine. Users only have to copy the design RTL source code and can start partitioning immediately, avoiding typical IT or software maintenance issues. The highest level of security is assured by Amazon AWS and the strict process of qualifying the AMI for the AWS Marketplace.

HES-DVM Proto CE can be used for prototypes containing up to four Xilinx FPGAs – present on off-the-shelf prototyping boards like Aldec HES, third party or even in-house-developed FPGA boards that are custom-made for a given project and provide features not available on commercial platforms. If a subsequent revision of the project grows and requires more than four partitions, there is a seamless migration path to the on-premises (standard licensed) version of HES-DVM, which can support any number of FPGAs.