Andes certifies Risc-V SIMD and DSP reference models

Update: August 6, 2023
Andes certifies Risc-V SIMD and DSP reference models

Cores carrying the P designation have SIMD and DSP extensions to the instruction set for data processing and real-time operation. “The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021,” according to Oxfordshire-based Imperas, which has also updated its simulation technology to accommodate P-capable cores. “Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.”

The Risc-V instruction set (ISA) is an open standard, and has a modular structure that includes multiple independent extensions suited to various applications, each carrying a letter designation – the ‘M’ extension adds multiplication and division, for example.

Multiple independent processing units can implement those extensions, interacting with each other and sharing peripherals, controlled by a mix of RTOS and non-real-time operating system running firmware and application software.

“RISC-V is a framework of flexibility – the real value is in the extensions and options available for processor core implementations,” according to Andes CTO Charlie Su. “The Risc-V P extension within the Andes cores addresses the real-time requirements in SIMD-DSP computations for markets in audio, speech, IoT, tinyML and edge devices.”

Imperas’ simulation tools run virtual models of Risc-V core hardware, allowing different hardware-software balances to be tested before committing to silicon.

“These virtual prototypes also support early software development, often many months before silicon prototypes are available,” said Imperas. “For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code. The Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.”

Earlier this month SiFive approved Imperas Risc-V simulation models