Avery Design extends collaboration with Rambus
Avery Design Systems, a specialist in functional verification solutions, is extending their long-term memory model and PCIe Verification IP (VIP) collaboration with Rambus.
Rambus uses Avery’s high-quality, full-featured memory models to verify its memory controllers including HBM2/2E, GDDR6, LPDDR4, and DDR3/4.
Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification. Rambus uses Avery’s PCIe VIP to verify its PCIe 5.0/4.0 controllers, including Endpoint, Root Port and Retimer modes, and PHYs.
“Avery’s cutting-edge VIP has enabled Rambus to verify controllers which support the most advanced features needed by customers in their current and next-generation designs,” said Brian Daellenbach, senior director of Digital Controllers, IP Cores at Rambus. “The collaboration between Avery and Rambus has helped both companies offer fully-verified IP solutions addressing the latest market requirements.”
“Rambus and Avery are both focused on creating best-in-class, robust, pre-validated memory and PCIe IP solutions which streamline the design and verification process for our customers. We look forward to continuing our collaboration to address the current and next-generation protocols being used by the market,” said Chris Browy, vice president sales/marketing of Avery.