“A large majority of edge compute, computer vision and industrial control algorithms are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware,” according to the company.
Called SmartHLS, the tool allows C++ algorithms to be directly translated to FPGA-optimised RTL (register transfer level) code.
It is based on the open-source Eclipse integrated development environment and uses C++ software code to generate an HDL IP (hardware design language intellectual property) component for integration into Microchip’s Libero SmartDesign projects.
In detail, the user implements their design in C++ software and verifies the functionality with software tests. Next, LegUp compiles the C++ program into functionality-equivalent Verilog hardware modules.
SmartHLS can run co-simulation with Modelsim to verify cycle-accurate behaviour hardware behaviour and confirm the hardware functionality matches the software, and it can generate the hardware IP cores for integration into larger systems by SmartDesign. LegUp can also run Libero synthesis on the generated Verilog to determine the FPGA area and Fmax. As well as PolarFire, the tool supports SmartFusion2 FPGAs.
“Writing C++ software code is easier for engineers than designing in RTL because software code is more concise, with 5-10X less lines of C++ required than RTL,” said Microchip. “Software is also easier to understand and modify for future improvements or maintenance compared to RTL. Software conciseness and readability mean less bugs in your FPGA design.”
The SmartHLS product page is here