It is called ‘Integrity 3D-IC’ and is said underpin the company’s third-generation 3D IC solution, providing power, performance and area for individual chiplets through integrated thermal, power and static timing analysis capabilities.
“Cadence has historically offered customers 3D IC packaging solutions through its digital, analogue and package implementation product lines,” said Cadence general manager Chin-Chi Teng. “With recent developments in packaging, we saw a need to provide a more tightly integrated platform that ties our implementation technology with system-level planning and analysis.”
System planning, electrothermal, static timing analysis and physical verification flows are brought together. It also incorporates 3D exploration flows, taking 2D netlists to create multiple 3D stacking scenarios based on user input “automatically selecting the optimal 3D stacked configuration”, claimed the company.
Co-design is possible with package design teams and out-sourced companies using Cadence Allegro packaging and the Virtuoso design environment.