Both aimed at of multi-billion-gate SoC designs, Palladium Z2 Enterprise Emulation is for pre-silicon hardware debug, and Protium X2 Enterprise Prototyping is for pre-silicon software validation. They follow on from Palladium Z1 and Protium X1.
Based on Xilinx UltraScale+ VU19P FPGAs, “these systems provide customers with 2x capacity and 1.5x performance improvements over their predecessors”, said Cadence. “Both systems offer modular compile technology capable of compiling 10 billion gates in under 10 hours on Palladium Z2 and in under 24 hours on Protium X2.”
A common front-end flow is shared allowing work load to be distributed between verification, validation and pre-silicon software bring-up. Debug is unified and there are common virtual and physical interfaces, and testbench.
“Xilinx and Cadence have worked closely to ensure the Cadence software front-end works seamlessly with the Xilinx Vivado Design Suite back-end,” said Xilinx director Hanneke Krekels. “The integrated Cadence and Xilinx front-to-back flow allows software developers to use the platform at the earliest possible point during the development flow and to focus on design validation and software development rather than prototype bring-up.”
Cadence’ verification full flow has the above tools plus Xcelium logic simulation, JasperGold formal verification platform and a suite of verification applications.