Cadence collaborates with Arm to accelerate SoC development

Cadence collaborates with Arm to accelerate SoC development

Cadence collaborates with Arm to accelerate SoC development

Cadence Design Systems is expanding its collaboration with Arm in a move intended to speed up hyperscale computing and 5G communications SoC development using Cadence tools and the Arm’s Neoverse V1 and Neoverse N2 platforms.

Cadence is looking to optimise its digital and verification full flows to drive adoption of these latest platforms and has already delivered comprehensive 5nm and 7nm RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) to help customers optimise power, performance and area (PPA) goals and improve productivity.

The integrated digital full flow from Cadence has been proven on a number of 5nm, 4GHz Neoverse V1 implementations and customers working on advanced-node designs, including 3D-IC chiplets, can use the new Cadence 5nm and 7nm RAKs to implement data centre server-class CPUs more efficiently and speed up time to tape-out.

The complete Cadence RTL-to-GDS RAKs include the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.

In addition to benefiting from Cadence’s proven 5nm, 4GHz digital full flow, companies building Arm Neoverse-based SoCs can also achieve improved SoC-level verification throughput by leveraging Cadence’s verification full flow. In particular, the Cadence System VIP solution has been enhanced with checkers, verification plans and traffic generators to verify Arm Neoverse-based SoC coherency, performance and Arm SystemReady compliance.

All Cadence verification engines are leveraged by these System VIP extensions to deliver a comprehensive SoC-level verification flow for Arm Neoverse-based SoCs.

“Arm and Cadence have a long history of collaborating on Arm IP development, with the Neoverse V1 and Neoverse N2 platforms being the most recent example,” said Dr. Chin-Chi Teng, senior VP and GM in the Digital & Signoff Group at Cadence.

“By evaluating past customer successes with the Neoverse N1 platform, we’ve successfully optimised the Cadence digital and verification full flows to create high-frequency, low-power, high-quality server-class designs using Arm’s newest infrastructure platforms. With the new 5nm and 7nm RAKs and System VIP tools, our data centre and 5G infrastructure customers can rapidly deliver innovative silicon solutions on schedule.”