Can Chiplet’s technology work for Moore’s Law to “continue life”?

There is a lot of heated discussion in the industry on the technical direction beyond Moore’s Law. The most popular one is to increase the density of transistors per unit area through more advanced processes. However, due to various considerations such as cost and technical difficulty, not all designs require high-end processes such as 7nm, 5nm or even 3nm. As the cost of monolithic integration continues to rise, many companies have begun to explore other options. Advanced packaging technologies such as 2.5D and 3D system-in-package (SiP) are popular options among them.

There is a lot of heated discussion in the industry on the technical direction beyond Moore’s Law. The most popular one is to increase the density of transistors per unit area through more advanced processes. However, due to various considerations such as cost and technical difficulty, not all designs require high-end processes such as 7nm, 5nm or even 3nm. As the cost of monolithic integration continues to rise, many companies have begun to explore other options. Advanced packaging technologies such as 2.5D and 3D system-in-package (SiP) are popular options among them.

At present, the industry is working hard to use advanced packaging technology to put multiple advanced or mature “chiplets” in one package (also known as heterogeneous integration), together with 3D packaging, to expand at the system level. law. This is the current hot technology in the Semiconductor industry-Chiplet.

What is Chiplet?

Chiplet is also called “small chip” or “core chip”, it is a kind of functional circuit block, including reusable IP block. For cost and yield considerations, a feature-rich and large-area chip die can be split into multiple small chips. These pre-produced small chips that can achieve specific functions are combined together, with the help of Advanced integration technologies (such as 3D packaging) are integrated and packaged together to form a system chip.

Chiplet technology has many advantages:

First, by dividing the large chip into smaller chips, the yield rate of production can be effectively improved and the manufacturing cost can be reduced.
Secondly, according to the needs of different IPs, suitable process nodes can be selected, which can significantly improve the manufacturing yield and further save costs-for example, digital IP can use high-end technology to achieve the high performance we expect, while analog IP can be selected more Economical and more mature process technology can also achieve the design effect.
There is also an outstanding advantage, that is, some proven and mature small chips can be reused, which not only reduces the design time and cost of the enterprise, but also effectively expands the enterprise’s resource library.

Of course, coins have two sides, and so does Chiplet. From the point of view of process node and yield, Chiplet’s manufacturing cost is definitely reduced, but because these small chips are separated in function (such as I/O control), its functions may be difficult to expand. In addition, if the large chip is divided into multiple small chips and then stacked, the cost of packaging may increase to a certain extent.

Why do you need Chiplet?

Before discussing why Chiplet is needed, let’s take a look at how much money the semiconductor manufacturing industry burns.

At the beginning of this year, Taiwan Semiconductor Manufacturing Company (TSMC) announced that it would significantly increase its 2021 capital expenditure budget to 25 to 28 billion U.S. dollars, and then further increase it to about 30 billion U.S. dollars. In TSMC’s investment, a larger part of the capital expenditure should be used to purchase EUV lithography machines. At the third quarter earnings conference of this year, ASML President and CEO Peter Wennink said: The company’s third quarter revenue reached 5.2 billion euros. The amount of new orders in the third quarter reached 6.2 billion euros, of which 2.9 billion euros came from EUV system orders, and customer demand for lithography systems is still at a high point. It is expected that the revenue in the fourth quarter of 2021 will be approximately 4.9 billion euros to 5.2 billion euros, and the research and development costs will be approximately 670 million euros. Samsung’s investment and efforts in the 5nm process node are obvious to all in the industry. Unfortunately, its yield rate is less than 50%, which has not reached expectations. Now the company is deploying expensive EUV lithography machines in the V1 production line of its Hwaseong factory. Improve yield. As the cost of chip manufacturing has risen sharply, not every company can afford to start chip tapeout costs of several hundred million yuan. SiP packaging technology integrates them together-this creates a demand for Chiplet SiP. Chiplet provides companies with an alternative method to create more advanced designs, with the most cost-effective solution, increasing the number of transistors designed to exceed the number that a single large chip can accommodate, achieving an “extra-molar” gain in the number of transistors. This is also an important reason why the industry has always had great expectations for Chiplet.

Chiplet evolution history

For many years, SiP technology has been the focus of the semiconductor packaging industry. Data from Yole shows that the SiP market is expected to increase from US$14 billion in 2020 to more than US$19 billion in 2026. Since the 1990s, SiP has appeared in the form of multi-chip modules (MCM). Although the definitions of various companies are somewhat different, the function is the same, that is, SiP can combine chips, passive devices, and even MEMS. Combine them together into one package. Chiplet can also be regarded as a kind of SiP technology, which is the chipization of IP modules in system-on-chip (SoC).

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 1: Roadmap for the evolution of advanced multi-chip packaging (Source: Cadence)

Both the SiP and Chiplet technologies solve the problem of increasing difficulty and cost of developing SoC on each new node. For Chiplet, suppliers or packaging and testing companies may therefore build a small chip IP library with various functions. In the long run, the company’s intellectual property rights will be greatly enriched. If these IPs are used for new product development, the time to market for products will be shortened.

Well-known supplier in the Chiplet market

In fact, Chiplet is not a completely new concept, as SiP, heterogeneous integration and MCM have existed for a long time. Many major chip manufacturers are strongly supporting this technology, AMD, Intel (Intel) and TSMC have announced or launched Chiplet products, but their implementation will be different.

TSMC Chiplet solution

TSMC proposed a bumpless system integrated chip (SoIC).As a Chiplet solution, SoIC is a 3D structure that is stacked by logic, memory or two types of chips on an active interposer with TSV. It adopts a chip-on-wafer (CoW) process and can handle inter-chips.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 2: Comparison of the characteristics of bump and non-bump technology and SoIC package (Source: TSMC)

AMD Chiplet solution

AMD’s current Chiplet solution uses laminated substrates, and has launched multiple versions of server processors based on Chiplet technology. At Computex this year, AMD released an experimental product of 3D V-Cache based on 3D Chiplet technology. It uses TSMC’s 3D Fabric packaging technology to package Chiplet with 64MB L3 Cache in a 3D stack with the processor. At the system level, it is like a monolithic chip. This new architecture will significantly improve the performance of the processor, and will not bring more power consumption, which cannot be achieved by monolithic integration.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 3: AMD’s 3D V-Cache processor based on 3D Chiplet technology (Source: AMD)

Intel Chiplet solution‍

Intel’s Chiplet solution is called Foveros. As a form of heterogeneous system integration, Foveros technology will provide designers with greater flexibility, enabling them to mix and match IP blocks with various memory and I/O elements. Next. Intel expects to use this technology in many product lines.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 4: Foveros technology with 3D face-to-face stacking (Source: Intel)

Concluding remarks

Before 2019, the commercialization of high-performance packaging in DRAM, HBM and FPGA is very strong, mainly used in the manufacture of various processors, including processor cores, SSDs, memory blocks, and CPUs and GPUs in graphics applications. . According to Yole’s report, the high-end packaging market is valued at US$871 million in 2019 and is expected to reach US$4.3 billion by 2025, with a compound annual growth rate of 31% from 2019 to 2025.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 5: High-end semiconductor packaging and testing market forecast (Source: Yole)

In recent years, reports about “Moore’s Law is dead” have been frequently reported. Now, the semiconductor industry has entered a new era, during which advanced packaging technology will play an increasingly important role, because the industry can no longer rely solely on monolithic integration to achieve higher performance while maintaining Higher economic benefits. Chiplet is a heterogeneous integrated solution, which is taking us into the next semiconductor era. At that time, Moore’s Law is expected to continue in a new way or way.

There is a lot of heated discussion in the industry on the technical direction beyond Moore’s Law. The most popular one is to increase the density of transistors per unit area through more advanced processes. However, due to various considerations such as cost and technical difficulty, not all designs require high-end processes such as 7nm, 5nm or even 3nm. As the cost of monolithic integration continues to rise, many companies have begun to explore other options. Advanced packaging technologies such as 2.5D and 3D system-in-package (SiP) are popular options among them.

At present, the industry is working hard to use advanced packaging technology to put multiple advanced or mature “chiplets” in one package (also known as heterogeneous integration), together with 3D packaging, to expand at the system level. law. This is the current hot technology in the semiconductor industry-Chiplet.

What is Chiplet?

Chiplet is also called “small chip” or “core chip”, it is a kind of functional circuit block, including reusable IP block. For cost and yield considerations, a feature-rich and large-area chip die can be split into multiple small chips. These pre-produced small chips that can achieve specific functions are combined together, with the help of Advanced integration technologies (such as 3D packaging) are integrated and packaged together to form a system chip.

Chiplet technology has many advantages:

First, by dividing the large chip into smaller chips, the yield rate of production can be effectively improved and the manufacturing cost can be reduced.
Secondly, according to the needs of different IPs, suitable process nodes can be selected, which can significantly improve the manufacturing yield and further save costs-for example, digital IP can use high-end technology to achieve the high performance we expect, while analog IP can be selected more Economical and more mature process technology can also achieve the design effect.
There is also an outstanding advantage, that is, some proven and mature small chips can be reused, which not only reduces the design time and cost of the enterprise, but also effectively expands the enterprise’s resource library.

Of course, coins have two sides, and so does Chiplet. From the point of view of process node and yield, Chiplet’s manufacturing cost is definitely reduced, but because these small chips are separated in function (such as I/O control), its functions may be difficult to expand. In addition, if the large chip is divided into multiple small chips and then stacked, the cost of packaging may increase to a certain extent.

Why do you need Chiplet?

Before discussing why Chiplet is needed, let’s take a look at how much money the semiconductor manufacturing industry burns.

At the beginning of this year, Taiwan Semiconductor Manufacturing Company (TSMC) announced that it would significantly increase its 2021 capital expenditure budget to 25 to 28 billion U.S. dollars, and then further increase it to about 30 billion U.S. dollars. In TSMC’s investment, a larger part of the capital expenditure should be used to purchase EUV lithography machines. At the third quarter earnings conference of this year, ASML President and CEO Peter Wennink said: The company’s third quarter revenue reached 5.2 billion euros. The amount of new orders in the third quarter reached 6.2 billion euros, of which 2.9 billion euros came from EUV system orders, and customer demand for lithography systems is still high. It is expected that the revenue in the fourth quarter of 2021 will be approximately 4.9 billion euros to 5.2 billion euros, and the research and development costs will be approximately 670 million euros. Samsung’s investment and efforts in the 5nm process node are obvious to all in the industry. Unfortunately, its yield rate is less than 50%, which has not reached expectations. Now the company is deploying expensive EUV lithography machines in the V1 production line of its Hwaseong factory. Improve yield. As the cost of chip manufacturing has risen sharply, not every company can afford to start chip tapeout costs of several hundred million yuan. SiP packaging technology integrates them together-this creates a demand for Chiplet SiP. Chiplet provides companies with an alternative method of creating more advanced designs, with the most cost-effective solution, increasing the number of transistors designed to exceed the number that a single large chip can accommodate, achieving an “extra-molar” gain in the number of transistors. This is also an important reason why the industry has always had great expectations for Chiplet.

Chiplet evolution history

For many years, SiP technology has been the focus of the semiconductor packaging industry. Data from Yole shows that the SiP market is expected to increase from US$14 billion in 2020 to more than US$19 billion in 2026. Since the 1990s, SiP has appeared in the form of multi-chip modules (MCM). Although the definitions of various companies are somewhat different, the function is the same, that is, SiP can combine chips, passive devices, and even MEMS. Combine them together into one package. Chiplet can also be regarded as a kind of SiP technology, which is the chipization of IP modules in system-on-chip (SoC).

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 1: Roadmap for the evolution of advanced multi-chip packaging (Source: Cadence)

Both the SiP and Chiplet technologies solve the problem of increasing difficulty and cost of developing SoC on each new node. For Chiplet, suppliers or packaging and testing companies may therefore build a small chip IP library with various functions. In the long run, the company’s intellectual property rights will be greatly enriched. If these IPs are used for new product development, the time to market for products will be shortened.

Well-known supplier in the Chiplet market

In fact, Chiplet is not a completely new concept, as SiP, heterogeneous integration and MCM have existed for a long time. Many major chip manufacturers are strongly supporting this technology, AMD, Intel (Intel) and TSMC have announced or launched Chiplet products, but their implementation will be different.

TSMC Chiplet solution

TSMC proposed a bumpless system integrated chip (SoIC).As a Chiplet solution, SoIC is a 3D structure that is stacked by logic, memory or two types of chips on an active interposer with TSV. It adopts a chip-on-wafer (CoW) process and can handle inter-chips.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 2: Comparison of the characteristics of bump and non-bump technology and SoIC package (Source: TSMC)

AMD Chiplet solution

AMD’s current Chiplet solution uses laminated substrates, and has launched multiple versions of server processors based on Chiplet technology. At Computex this year, AMD released an experimental product of 3D V-Cache based on 3D Chiplet technology. It uses TSMC’s 3D Fabric packaging technology to package Chiplet with 64MB L3 Cache in a 3D stack with the processor. At the system level, it is like a monolithic chip. This new architecture will significantly improve the performance of the processor, and will not bring more power consumption, which cannot be achieved by monolithic integration.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 3: AMD’s 3D V-Cache processor based on 3D Chiplet technology (Source: AMD)

Intel Chiplet solution‍

Intel’s Chiplet solution is called Foveros. As a form of heterogeneous system integration, Foveros technology will provide designers with greater flexibility, enabling them to mix and match IP blocks with various memory and I/O elements. Next. Intel expects to use this technology in many product lines.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 4: Foveros technology with 3D face-to-face stacking (Source: Intel)

Concluding remarks

Before 2019, the commercialization of high-performance packaging in DRAM, HBM and FPGA is very strong, mainly used in the manufacture of various processors, including processor cores, SSDs, memory blocks, and CPUs and GPUs in graphics applications. . According to Yole’s report, the high-end packaging market is valued at US$871 million in 2019 and is expected to reach US$4.3 billion by 2025, with a compound annual growth rate of 31% from 2019 to 2025.

Can Chiplet’s technology work for Moore’s Law to “continue life”?
Figure 5: High-end semiconductor packaging and testing market forecast (Source: Yole)

In recent years, reports about “Moore’s Law is dead” have been frequently reported in newspapers. Now, the semiconductor industry has entered a new era, during which advanced packaging technology will play an increasingly important role, because the industry can no longer rely solely on monolithic integration to achieve higher performance while maintaining Higher economic benefits. Chiplet is a heterogeneous integrated solution, which is taking us into the next semiconductor era. At that time, Moore’s Law is expected to continue in a new way or way.

 

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