The process, compared to 7nm, improves performance by 45% at the same power, or 75% energy at the same performance.compared to modern 7nm processors.
The 3-stack GAA transistor has a cell height of 75 nm, a cell width of 40 nm, and the individual nanosheets are 5nm in height, separated from each other by 5 nm. The gate poly pitch is 44nm, and the gate length is 12 nm.
The design uses bottom dieletric isolation channels, which enables the 12 nm gate length, and that its inner spacers are a second generation dry process design that help enable nanosheet development.
IBM uses EUV patterning on the FEOL parts of the process, enabling EUV at all stages of the design for critical layers.
IBM says that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations. Wafer up close
The chip was designed and made at IBM’s Albany research facility.