IP test silicon for PCI Express 6.0 specification on TSMC’s N5 process

IP test silicon for PCI Express 6.0 specification on TSMC’s N5 process

IP test silicon for PCI Express 6.0 specification on TSMC's N5 process

Cadence Design Systems is making IP immediately available that supports the PCI Express (PCIe) 6.0 specification on the TSMC N5 process.

The IP consists of a high-performance DSP-based PHY and a feature-rich companion controller to deliver the optimised performance and throughput for next-generation applications in hyperscale computing and 5G communications, including networking, emerging memory and storage. Early adopters can access design kits now.

The 5nm PCIe 6.0 PHY test chip silicon from Cadence demonstrated excellent electrical performance across all PCIe rates and the PAM4/NRZ dual-mode transmitter delivered optimal signal integrity, symmetry and linearity with extremely low jitter.

The DSP-based receiver demonstrated robust data recovery capabilities while withstanding harsh signal impairments and channel loss in excess of 35dB at 64GT/s. In addition, the advanced DSP core in the PHY is able to provide continuous background adaptation to monitor and compensate for the signal fluctuations induced by environmental factors, achieving enhanced reliability.

The Cadence controller IP for PCIe 6.0 is designed to provide the highest link throughput and utilization while operating with extremely low latency. A highly scalable multi-packet processing architecture supports up to 1024-bit wide data path in x16 configuration while operating at 1GHz to achieve maximum aggregate bandwidth of 128Gbps. The controller IP supports all the new PCIe 6.0 features, including PAM4 signalling, Forward Error Correction (FEC), FLIT Encoding and L0p power state while retaining full backward compatibility.

A PCIe 6.0 subsystem test chip was taped out on TSMC N5 in July 2021 and this integrated the second-generation power, performance and area (PPA)-optimised PCIe 6.0 PHY together with the PCIe 6.0 controller. This subsystem test chip enables Cadence to validate PCIe 6.0 PHY and controller functions at the system level and perform rigorous compliance and stress tests to ensure universal interoperability and reliability.

“We work closely with Cadence to enable next-generation designs benefiting from the significant power, performance and area improvements of our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “This collaborative effort combining Cadence’s leading IP solution with TSMC’s 5nm technology will help our mutual customers meet the most challenging power and performance requirements and quickly launch their differentiated product innovations.”

“Early adopters have already started exploring with the new PCIe6 specification, and we are looking forward to seeing them achieve positive results with TSMC and Cadence technologies,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “We’ve been deploying PAM4-based IP since 2019 when we introduced our first-generation 112G-LR SerDes IP, and our expertise in PAM4 technology plus our strong collaboration with TSMC provides a robust foundation for success with our PCIe6 products.”