Microchip targets military and industrial systems with chip scale atomic clock

Update: August 20, 2021

Microchip targets military and industrial systems with chip scale atomic clock

Microchip targets military and industrial systems with chip scale atomic clock

Microchip Technology has unveiled the SA65, a chip scale atomic clock (CSAC) that provides precise timing accuracy and stability in extreme environments.

Advanced military platforms, ocean-bottom survey systems and remote sensing applications all require precise timing. CSACs ensure stable and accurate timing even when Global Navigation Satellite Systems (GNSS) time signals are unavailable.

The SA65 CSAC is an embedded timing solution with improved environmental ruggedness, delivering higher performance than the previous SA.45s CSAC, including double the frequency stability over a wider temperature range and faster warm-up at cold temperatures.

The device has an operating temperature range of -40 to 80C and a storage temperature range of -55 to 105C. The warm-up time of two minutes at -40 oC is 33% faster than that of the SA.45s.

These various performance improvements will benefit designers of highly-portable solutions for military applications such as Assured Position, Navigation and Timing (A-PNT) and command, control, communications, computers, cyber, intelligence, surveillance and reconnaissance (C5ISR) requiring precise frequencies generated by a low Size, Weight and Power (SWaP) atomic clock. Improvements such as fast warm-up to frequency after cold start, temperature stability over a wide operating range, and frequency accuracy and stability enabling extended operation while GNSS is denied help to ensure mission success in conflict environments.

The SA65 CSAC is the world’s lowest-power commercial atomic clock and provides precise timing for portable and battery-powered applications requiring continuous operation and holdover in GNSS-denied environments. The SA65 is form-, fit- and function-compatible with the SA.45s, which minimises risk and redesign costs for the system developer while improving performance and environmental insensitivity.