New SiC diodes deliver highest efficiency and superior robustness

Update: May 12, 2023

Navitas Semiconductor now offers its fifth generation of high-speed GeneSiC SiC power diodes for demanding data centre, industrial motor-drive, solar and consumer applications.

The 650V-rated Merged-PiN Schottky (MPS) diodes incorporate a unique PiN-Schottky structure, providing ‘low-built-in voltage-biasing’ (‘low knee’) for the highest efficiency across all load conditions with excellent robustness. Applications include PFC in server/telecom power supplies, industrial motor drives, solar inverters, LCD/LED TVs, and lighting.

“We’re delivering reliable, lead-edge performance for in-demand applications like AI and Chat GPT data centre power,” noted Dr Ranbir Singh, Navitas EVP for SiC. “Efficient, cool, dependable operation ensures long lifetimes and brings peace-of-mind to power designers and optimises their time-to-prototype and time-to-market.”

The novel design incorporates the best features of PiN and Schottky diode structures, delivering the lowest forward-voltage (VF) drop of only 1.3V, high surge-current capability (IFSM), and minimised temperature-independent switching losses. Proprietary thin-chip technology further decreases VF and enhances thermal dissipation for cooler operation. These diodes are being provided in a low-profile surface mount QFN package for the first time.

To provide reliable operation in critical applications, the gen-5, 650V MPS diodes deliver best-in-class robustness and ruggedness, high surge-current and avalanche capability, and 100% avalanche (UIL) production testing.

Varying from 4A to 24A capability, in an array of surface-mount (QFN, D2-PAK) and through-hole (TO-220, TO-247) packaging, the GExxMPS06x-series MPS diodes cover applications ranging from 300W to 3,000W and various circuits such as solar panel boost converters, and continuous-current mode PFC in gaming consoles. With a ‘common-cathode’ configuration, the TO-247-3 package delivers great flexibility for high power density and bill-of-material reduction in interleaved PFC topologies.

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