Performance characteristics of PCI9052 interface chip and analysis of application examples

Update: March 23, 2024

The PCI bus protocol is very complicated. If you develop a PCI expansion board and use a programmable logic array chip to complete the implementation of the PCI protocol, the workload and difficulty are huge, and PCI dedicated interface chips are generally used. The PCI9052 interface chip is introduced below.

Author: Wei Wenhua

PCI (Peripheral Component Interconnect) bus is a local bus that can provide a high-performance data bus for the main CPU and peripherals. In 1992, many groups led by INTEL began to design the PCI bus, and its V2.0 specification was officially released in April 1993. The PCI bus has strict specifications, which ensures that it has good compatibility. Expansion cards that comply with the PCI specification can be inserted into any PCI system to work reliably; the PCI bus can provide a very high data transfer rate (132MB/S); PCI The bus has nothing to do with the CPU, and has nothing to do with the clock frequency. It can be applied to various platforms and supports multi-processors and concurrent work. The PCI bus also has good scalability. Through the PCI-PCI bridge, it can allow unlimited expansion; PCI bus It replaces the VESA local bus with its plug-and-play feature. A PCI interface includes a series of registers. The information in these registers allows the computer to automatically configure the PCI card. The PCI bus is currently the most advanced bus on the PC.

The PCI bus protocol is very complicated. If you develop a PCI expansion board and use a programmable logic array chip to complete the implementation of the PCI protocol, the workload and difficulty are huge, and PCI dedicated interface chips are generally used. The PCI9052 interface chip is introduced below.

1 PCI9052 chip introduction

PCI9052 is an interface chip developed by PLX Technology Company for expansion adapter boards that can provide a hybrid high-performance PCI bus target (slave) mode. The chip can be connected to a variety of local buses, and supports a relatively slow local bus with a burst transfer rate of 132MB/S on the PCI bus. The 9052’s programmable configuration is directly connected to the multiplexed or non-multiplexed 8/16/32-bit local bus. The 8-bit and 16-bit modes facilitate the direct conversion of ISA cards to PCI cards.

1.1 Main features

(1) Compatible with PCI V2.1 protocol features. The 9052 chip is compatible with PCI protocol V2.1 and supports low development cost slave mode adapter devices. The chip supports conversion from ISA adapter cards to PCI adapter cards.

(3) Interrupt generator. 9052 can generate a PCI interrupt from two local bus interrupt inputs.

(4) Clock. The 9052 local bus interface runs on the TTL clock and generates the necessary internal clock. The local TTL clock works asynchronously with the PCI clock and allows the local bus to work independently of the PCI clock. The buffered PCI bus clock BCLKO can be connected to the local bus clock LCLK.

(5) Programmable local bus configuration. 9052 supports multiplexed or non-multiplexed 8/16/32bit local bus. The chip has 4 bytes to enable, 26 address lines, and 32/16/8bit data lines.

(6) Read first mode. The 9052 supports the read-first mode, that is, the pre-latched data can be read from the 9052 internal FIFO register before the local bus.

(7) Bus driver. All control, address and data signals are directly generated by 9052, which are used to drive PCI and local buses without additional drive circuits.

(8) Serial EEPROM interface. 9052 contains a serial EEPROM interface for loading configuration information, for loading a specific adapted device information? This is very useful. Serial EEPROM is also necessary when converting 9052 to ISA interface mode.

(9) Four local chip select signals. 9052 provides four local chip select signals, the base address and the range of each chip select can be independently programmed by serial EEPROM or the main controller

(10) Five local address spaces. The base address and the range of each local address space can be independently programmed by the serial EEPROM or the main controller.

(11) Read/write storage delay and write cycle retention. For the ISA bus, the read/write signal can be delayed from the beginning of the clock cycle.

(12) Local bus waiting state. The additional LRDYi handshake signal is used to generate various wait states, and the 9052 has an internal wait state generator.

(13) Programmable pre-latch counter. The local bus pre-latch counter can be programmed as 0 (no pre-latch), 4, 8, 16 or continuous value (pre-latch counter off) mode.

1.2 Pin function

PCI9052 is a 160-pin plastic PQFP package structure. The functions of each pin are listed in Table 1 to Table 7 according to functional blocks.

2 The use of PCI9052 chip

PCI9052 interface chip as a general PCI interface, its application occasions and scope are extensive. With the gradual decrease in the number of ISA expansion slots in PCs until they are cancelled, PCI expansion slots have become the mainstream of PC motherboard configuration, and the development of future expansion boards must be based on the PCI interface.

However, many existing expansion boards with ISA interfaces, especially the expansion boards with some special functions independently developed by myself, how to make them continue to be used in the PCI slot, seem to be very meaningful. The following focuses on the application of the PCI9052 interface chip to directly convert the ISA expansion board to the PCI expansion board.

2.1 Introduction to ISA interface mode

The internal structure of PCI9052 contains an independent ISA logic interface, through which the smooth conversion from ISA to PCI can be completed. It supports ISA devices with 8-bit and 16-bit data widths, which can be memory mapped or I/O mapped. The read-first mode is used to improve the throughput of reading data. Once the ISA interface mode is enabled, PCI9052 only performs a single cycle operation. In particular, the serial EEPROM must enable the ISA interface mode.

2.1.1 Configuration method

There are two ways to configure PCI9052 for ISA interface mode.

Method 1: Burning serial EEPROM method. Use the writer to write the data into the serial EEPROM, refer to Table 8 to use the appropriate data. It should be noted that, for the ISA mode, the LRESET# (132) pin must always be high, and confirm that the MODE (68) pin is set to 0, which is in non-multiplexed mode.

Method 2: Thermal configuration method. Use the same data of method one to program serial EEPROM from PCI bus through PCI9052 chip. This method needs to pay attention to that the polarity of the LRESET# (132) pin changes from low to high in ISA mode, and confirm that the MODE (68) pin is set to 0.

2.1.2 Configuration Notes

When configuring for ISA interface mode, you must pay attention to the following points:

①When accessing ISA interface pins, please refer to the C/ISA mode pin diagram of PCI9052 pin to connect.

②Space 0 is allocated to the memory access of the ISA interface.

③Space 1 is allocated for I/O access of the ISA interface.

④ No matter the local address of space 0 is in the range of CS0# or the local address of space 1 is in the range of CS1#, ISA access is valid.

⑤The standard slave cycle can use space 2, space 3 and serial EEPROM to access.

2.2 Application examples

An application example of an Electronic transfer switch controller is given below. The function of the controller is to send a control code C0H to the port 200H when a trigger condition is detected to control the Relay to complete the switching action. This example is intended to illustrate how to use PCI9052 to convert from ISA expansion board to PCI expansion board.

2.2.1 Hardware design

The hardware circuit structure diagram of the controller is shown as in Fig. 1.

The circuit is divided into three parts. The first part is the connection signal line between 9052 and PCI slot. These signals include the address data multiplexing signal AD? 31:0? , The bus command signal C/BE? 3:0? # And PCI protocol control signals PAR, FRAME#, IRDY#, TRDY#, STOP#, IDSEL, DEVSEL#, PERR#, SERR#. The second part is the connection with the serial EEPROM. There are four signal lines: EESK, EEDO, EEDI and EECS. The serial EEPROM data can be burned in advance with a writer or online. The third part is the connection between 9052 and the application circuit. In this example, the ISA local bus signal is mainly used. Is there a data line LAD? 7:0, address line ISAA? 1:0? , LA? 23:2? , I/O read and write signal lines IOWR#, IORD#, address latch BALE.

2.2.2 Software design

The program is divided into two parts. One part assigns values ​​to each configuration register of PCI9052 and initializes the chip. The other part is the main program. The task is to continuously query the relevant key values ​​in the registry. Once the conditions are met, it sends control codes to the port. The program is completed in DELPHI language. The main reason for choosing DELPHI is that it can be compiled into an independent executable file without any dynamic link library, the program is short and powerful, and the compatibility between DELPHI versions is relatively good. The program flow chart is shown as in Fig. 2.

The Links:   SKIIP31NAB12T11 TPS24751RUVR