The rise of AI and big data has been fueling the trend toward heterogeneous computing, where multiple processors work in parallel to process massive volumes of data.
CXL — an open, industry-supported interconnect based on the PCI Express (PCIe) 5.0 interface — enables high-speed, low latency communication between the host processor and devices such as accelerators, memory buffers and smart I/O devices, while expanding memory capacity and bandwidth well beyond what is possible today.
Samsung has been collaborating with several data center, server and chipset manufacturers to develop next-generation interface technology since the CXL consortium was formed in 2019.
“This is the industry’s first DRAM-based memory solution that runs on the CXL interface,” claims Samsung vp Cheolmin Park.
Unlike conventional DDR-based memory, which has limited memory channels, Samsung’s CXL-enabled DDR5 module can scale memory capacity to the terabyte level, while reducing system latency caused by memory caching.
In addition to CXL hardware innovation, Samsung has incorporated several controller and software technologies like memory mapping, interface converting and error management, which will allow CPUs or GPUs to recognize the CXL-based memory and utilize it as the main memory.
Samsung’s new module has been successfully validated on next-generation server platforms from Intel, signaling the beginning of an era for high-bandwidth, low latency CXL-based memory using the latest DDR5 standard.
Samsung is also working with data centre and cloud providers around the world to better accommodate the need for greater memory capacity that will be essential in handling big data applications including in-memory database systems.
As the DDR5-based CXL memory module becomes commercialized, Samsung intends to lead the industry in meeting the demand for next-generation high-performance computing technologies that rely on expanded memory capacity and bandwidth.