He was talking about a 125 x 245μm integrated circuit die presented at the IEEE International Conference on RFID.
It has -2 dBm sensitivity in the 860-960MHz band and its small size is put down to “a largely standard cell-based digital implementation using dual-phase RF-only logic approach, near-threshold voltage operation and the elimination of area intensive, complex, and less scalable rectifiers, storage capacitors, and power management units used in conventional RFID tags” according to the presentation.
“The size of an RFID tag is largely determined by the size of its antenna, not the RFID chip,” said Franzon. “But the chip is the expensive part.” Being so small “in practical terms, this means that we can manufacture RFID tags for less than one cent each if we’re manufacturing them in volume”.
All but six cells were directly from the foundry’s standard cell library.
According to fellow researcher Kirti Bhanushali, the design of the circuits is compatible with a range of Semiconductor technologies and would allow RFID circuits to be included in alongside other circuits in valuable or critical ICs, for example.
“We’re now interested in working with industry partners to explore commercialising the chip in two ways: creating low-cost RFID at scale for use in sectors such as grocery stores, and embedding RFID tags into computer chips in order to secure high-value supply chains,” said Franzon.
The paper is ‘A 125μm×245μm mainly digital UHF EPC Gen2 compatible RFID tag in 55nm CMOS process‘ – scroll down to S3, abstract only available freely.