Sondrel modelling flow looks to cut ASIC modelling time

Modelling SoCs needs to be conducted well in advance in order to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run.

Detailed architectural modelling provides estimates of the performance, power, memory resources, and the NoC (Network on Chip) configuration that will be required along with an indicative size of the die and what it is likely to cost.

Sondrel has created proprietary modelling flow software, initially for use with Arm and Synopsys tools, that is able to dramatically reduce the time to do this from months to just a few days, which Sondrel claims to be an industry first for a services organisation.

While modelling tools are available as standard items from leading vendors Sondrel has wrapped those vendor offerings with its own custom flow. The vendor’s tools are limited in terms of automation and ways that they can be adjusted but Sondrel’s new modelling flow tool adds a framework with a much greater number of settings that can be tweaked by the Sondrel Systems Architect who is working on the project.

This is added using hooks into the vendor’s software that are provided for this very purpose. Typically, users create customisation wrappers that are specific to the designs that they work on if not already present in a library of an ever-growing number of such wrappers.

However, because Sondrel works on a wide variety of projects for a plethora of customers, it has defined a methodology and flows that are unique and broader in scope so that they can be used for almost any architectural exploration project.

The biggest benefit of the modelling flow’s dramatic reduction in the time it takes to create a model and run simulations, is that Sondrel can provide customers with data on the likely performance of a proposed ASIC in a matter of few days to determine if the architecture proposed gives an appropriate set of numbers.

If not, it is very easy and quick to run variants of the model simply by changing the settings of the existing model to decide which is the best one for the customer’s application usecase. Running each variation takes anywhere between a few minutes to an hour, so the whole process of model creation and running variants can still be done in the same timeframe.

For comparison, converging on a candidate architecture without Sondrel’s modelling flow tool would rely heavily on static spreadsheet modelling which would take several weeks and then each variant of the model to evaluate different architectures would each take weeks as each variant model would have to be created from scratch. Overall, that could total a number of months.

“In the rapidly moving world of electronic systems where time to market is critical and chip designs can cost millions, we are always developing new ways to give our customers huge advantages in this race,” explained Graham Curren, Sondrel’s CEO. “This enhanced architectural modelling is just one of many innovations that our extensive internal R&D programme has created for our turnkey service that enable us to rapidly provide customers with all the information that they need at the start of a project to understand all its aspects right through to cost per packaged, tested die.”