TSMC lays out a killer roadmap

Currently N3, which entered volume production in Q4 2022, is the most advanced process.

Following it up is N3E which has passed technology qualification and achieved its performance and yield targets. It has received the first wave of customer product tape-outs and will start volume production in the second half of 2023.

The number of new tape–outs for N3E is 1.5 to 2X that of N5 over the same period.

TSMC lays out a killer roadmap

Coming up are:

N3P, which offers additional performance and area benefits while preserving design rule compatibility with N3E to maximise IP re-use. It is scheduled to enter production in the second half of 2024 It will deliver 5% more speed at the same leakage, 5% to 10% power reduction at the same speed, and 1.04X more chip density compared with N3E.

N3X, which is tuned for HPC applications, provides extra Fmax gain to boost overdrive performance at a modest  trade-off with leakage. This translates to 5% more speed versus  N3P at drive voltage of 1.2V, with the same improved  chip density as N3P. N3X will enter volume production in 2025.

N3AE, which is the  industry’s first Auto Early technology on 3nm, offers automotive PDKs based on N3E and allows customers to launch designs on the 3nm node for automotive applications, leading  a fully automotive–qualified N3A process in 2025.

N2, which is based on the GAA nanosheet Transistor, for which volume production is targeted for 2025; N2P and N2X are planned for 2026.

The performance of the nanosheet Transistor has exceeded 80% of the company’s technology targets while demonstrating excellent power, efficiency and lower Vmin, says TSMC, which is great for energy–efficient computing.

TSMC has exercised N2 design collateral in the physical implementation of an Arm A715 CPU core to measure PPA improvement: it achieved a 30% speed gain at the same power, or 33% power reduction at the same speed at around 0.9V, compared to the N3E, high-density, 2-to-1, fin standard cell.

Part of the TSMC technology platform – a backside power rail – provides an additional speed and density boost on top of the baseline technology

The backside power rail is best suited for HPC products and will be available in the second half of 2025.

The technology improves speed by more than 10-12% from reducing IR drop and signal RC delays and reduces the frontside area required for logic by 10-15%.

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