The heterogeneous integration roadmap (HIR) is an ongoing initiative of the IEEE Electronics Packaging Society. It’s a living document that continues to evolve and expand in response to technological developments like the growth of generative artificial intelligence (AI) and quantum computing.
This FAQ starts with a brief overview of heterogeneous integration, looks at the scope of the HIR, and closes by considering how the HIR is evolving to accommodate the needs of quantum computing.
Heterogeneous integration (HI) is the use of a variety of components from different manufacturers housed in a single package; it’s sometimes referred to as a system-in-package (SiP) (Figure 1). HI can overcome the yield limitations of large ASICs, support a mix-and-match strategy for heterogeneous semiconductor IPs and multiple process nodes, and support enhanced functionality like improved thermal performance, smaller solution sizes, and speed time to market. Until now, HI and chiplets have been developed by large manufacturers using proprietary technologies. The HIR from the IEEE seeks to democratize heterogeneous chiplet development.
HIR scope
The scope of the IEEE HIR is to address the assembly and packaging needs of advanced systems like generative AI and HPC. It’s expected to identify difficult technical challenges and potential solutions for advanced technologies like chiplets and SiP. The key purpose of the HIR is to provide a guideline for the global electronics industry of projected technology needs and opportunities for innovation — without regard to any commercial considerations.
The field addressed by the HIR includes materials, thermal management, power management, high-performance interconnects, processes, and equipment needed for multi-device heterogeneous integration of diverse devices to support improvements in performance, reliability, cost, and time to market. It’s also expected that one or more of the dies used in a chiplet will be fabricated using a leading-edge IC process node.
Incorporating a wide array of technologies like digital processors and memories, wireless and mixed signal devices, analog ICs, power devices, optoelectronics, MEMS, sensors, and even biochips in a single package is expected to support smaller and more optimized solutions. The HIR recognizes that meeting the needs of advanced technologies like generative AI and machine learning (ML) is increasingly difficult due to the slowing of Moore’s Law scaling for CMOS. Chiplets and the HIR are expected to address those challenges.
The challenges addressed by the HIR are often referred to as “advanced packaging” and include an array of technologies for the design, processing, assembling, and testing of chiplets to enable cost, performance, power, thermal, and size optimization. Advanced packaging encompasses a broad range of technologies, including flip-chip on substrates, wafer-scale packaging, and the use of interposers with or without through-hole silicon vias (TSVs). It also includes lateral (2D and 2.5D) and vertical (3D) structures. With its long-term, 15-year perspective, HIR is considering potential needs beyond today’s systems, like the emerging area of quantum computing.
HIR and quantum computing
The HIR is investigating possible applications for chiplets in quantum computing, beginning by looking at the building blocks of a generic quantum computer. Those building blocks include the host processor that interfaces with application software and the outside world, the control plane that directs the control/management plane to set qubit states, and the control/management plane that interacts with the qubit data plane where quantum computing takes place (Figure 2).
The control/management plane has been identified as a good place to use HI and chiplets. It is usually in a space-constrained environment and includes both analog and digital functions. The digital components can benefit from using different process technologies for specific functions. The analog devices that communicate with the qubits using microwave signals can connect through waveguides fabricated in the interposer. The use of chiplets is also expected to simplify thermal management, an important consideration in quantum computers. Finally, as the qubit count rises in the future, chiplets can support modular designs that can be easily and quickly scaled.
Summary
The IEEE HIR has a long-term view of technological developments related to chiplets and advanced packaging. It’s intended to provide near-term and long-term guidelines to identify opportunities for technology and innovation in all the technologies needed to support heterogeneous integration and chiplets. Its charter also includes the development of chiplets for emerging technologies like quantum computing.
References
Heterogeneous Integration (HI), ASE Technology
Heterogeneous Integration and Chiplet Assembly—all Between 2D and 3D, IEEE
Heterogeneous Integration Roadmap, IEEE Electronics Packaging Society
Heterogeneous Integration Roadmap, Chapter 2: High Performance Computing and Data Centers, IEEE Electronics Packaging Society