How Busbar Support Capacitor ESL/ESR Affects IGBT Turn-off Voltage Spikes: A PCB & Laminated Busbar Design Guide

The Unseen Enemy: Why Parasitic Inductance is Critical in High-Power Systems

In modern power electronics, particularly in applications like EV inverters, solar converters, and industrial motor drives, Insulated Gate Bipolar Transistors (IGBTs) are switched at increasingly high frequencies to improve efficiency and power density. However, this high-speed switching introduces a significant challenge: voltage overshoot during turn-off. This transient voltage spike, superimposed on the DC bus voltage, can exceed the IGBT’s breakdown voltage, leading to catastrophic failure. The root cause of this dangerous phenomenon lies in an often-overlooked electrical property: parasitic inductance.

Every conductor in a circuit, from the internal bond wires of an IGBT module to the traces on a Printed Circuit Board (PCB) and the DC link capacitors, possesses a small amount of inductance. While negligible at low speeds, this “stray” or “parasitic” inductance becomes a major problem when current changes rapidly (high di/dt). The DC link capacitor, crucial for stabilizing the bus voltage and supplying high-frequency ripple currents, is a key component in this dynamic. Its own parasitic characteristics—Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR)—play a direct role in the magnitude of the turn-off voltage spike.

Deconstructing the Problem: The Physics of Turn-off Voltage Spikes

The Formula That Governs It All: V = L * (di/dt)

The relationship between parasitic inductance and voltage overshoot is defined by a fundamental law of physics: V = L * (di/dt). Here:

• V is the induced voltage spike (overshoot).
• L is the total parasitic inductance in the commutation loop.
• di/dt is the rate of change of current as the IGBT turns off.

This formula clearly shows that for a given switching speed (di/dt), the voltage spike is directly proportional to the total loop inductance. When an IGBT turns off, the current flowing through it rapidly drops to zero. This abrupt change interacts with the total inductance of the path between the DC link capacitor and the IGBT module—known as the commutation loop—generating a significant voltage spike. Understanding and minimizing this loop inductance is therefore the primary goal for any high-performance power stage design.

The Culprits: ESR and ESL in DC Link Capacitors

An ideal capacitor would only have capacitance, but real-world components have parasitic elements that affect their performance. For DC link capacitors, the two most important are ESR and ESL.

• Equivalent Series Resistance (ESR): This represents the total resistive losses within the capacitor. High ESR leads to power dissipation (I²R losses), causing the capacitor to heat up and reducing overall system efficiency. While ESR is a critical parameter for thermal management, it has a less direct impact on the peak voltage spike compared to ESL.
• Equivalent Series Inductance (ESL): This is the parasitic inductance inherent in the capacitor’s physical construction—the leads, internal plates, and terminals. In the context of turn-off spikes, the capacitor’s ESL is a direct contributor to the total loop inductance (L) in the V = L * (di/dt) equation. Capacitors with lower ESL are essential for mitigating voltage overshoot.

The Source of the Stray Inductance: A System-Wide View

The total commutation loop inductance is the sum of inductances from several sources. To effectively control it, engineers must analyze the entire current path from the DC link capacitor, through the power bus structure, into the IGBT module, and back again.

Component-Level Inductance

Both the IGBT module and the capacitor have internal parasitic inductance. Power module manufacturers have made significant strides in reducing internal stray inductance to values as low as 5-10 nH through optimized internal layouts and terminal designs. Likewise, capacitor manufacturers offer specialized low-ESL designs, often with film dielectrics and laminated internal structures, that can bring internal ESL down to a few nanohenries.

Layout-Level Inductance: PCB vs. Laminated Busbar

The most significant and often most controllable source of parasitic inductance comes from the physical connection between the DC link capacitor and the IGBT module.

• Traditional Wiring and PCBs: Using cables or long, thin PCB traces to connect the capacitor and IGBT creates a large current loop area. A larger loop area results in higher magnetic field storage and, consequently, higher inductance. For high-power, high-frequency systems, this approach is often inadequate and leads to excessive voltage overshoot.
• Laminated Busbars: A laminated busbar is the industry-standard solution for minimizing layout inductance. It consists of multiple layers of flat conductors (e.g., copper or aluminum) separated by a thin dielectric material. The positive and negative conductors are arranged in parallel, overlapping planes. This structure forces the current to flow in opposite directions in very close proximity, causing their magnetic fields to cancel each other out. This magnetic cancellation drastically reduces the overall inductance, often by an order of magnitude compared to traditional wiring. For a deeper dive into this topic, our article on The Impact of Parasitic Inductance on IGBT Switching Performance provides further analysis.

Practical Design Guide: Taming the Voltage Spike

Minimizing turn-off voltage overshoot requires a holistic approach that combines careful component selection with advanced layout techniques.

Strategy 1: Optimizing DC Link Capacitor Selection and Placement

The first line of defense is choosing the right capacitors and placing them correctly. A hierarchical approach is often best:

• Bulk Capacitors: Large electrolytic capacitors that provide the main energy storage but have high ESL and are slow to respond.
• Support (DC Link) Capacitors: High-quality film or ceramic capacitors with low ESL and ESR placed very close to the IGBT module. These supply the high-frequency switching currents.
• Local Decoupling Capacitors: Small ceramic capacitors, sometimes integrated directly into the power module, providing the lowest inductance path for the highest frequency components of the switching transient.

Placement is critical: The support capacitors must be located as physically close as possible to the IGBT power terminals to minimize the commutation loop area. Every millimeter of trace length adds inductance.

Strategy 2: Laminated Busbar Design Principles

When designing a laminated busbar, the goal is to maximize magnetic field cancellation. Key principles include:

• Maximize Overlap Area: The positive and negative conductor plates should overlap as much as possible.
• Minimize Dielectric Thickness: Using a thinner, high-quality insulating layer brings the opposing currents closer together, enhancing the cancellation effect and further reducing inductance.
• Minimize Loop Geometry: Keep the physical distance between the capacitor terminals and the IGBT terminals as short as possible.

A well-designed laminated busbar can reduce the interconnect inductance to just a few nanohenries, making it a crucial element in modern high-power converters.

Strategy 3: Advanced PCB Layout Techniques

If a full laminated busbar is not feasible, advanced PCB design can still significantly reduce inductance:

• Use Power Planes: Instead of thin traces, use wide, solid copper planes for the DC+ and DC- paths. Placing these planes on adjacent layers creates a structure similar to a laminated busbar, leveraging magnetic cancellation.
• Minimize Loop Area: Keep the high-frequency current return path directly underneath the forward path to minimize the physical area of the loop.
• Strategic Via Placement: Use multiple vias in parallel to reduce the inductance of connections between layers. Keep power and ground vias close together.

Comparative Analysis: PCB, Wires, and Laminated Busbars

The choice of interconnection technology has a profound impact on system performance. Below is a comparison of the different methods.

Parameter	Wires/Cables	Standard PCB Trace	Laminated Busbar / Optimized PCB Planes
Parasitic Inductance	Very High ( >100 nH)	Moderate to High (20-100 nH)	Very Low ( < 20 nH, often < 10 nH)
Current Carrying Capacity	Limited by wire gauge	Limited by trace width and copper thickness	Very High, easily customized
Thermal Management	Poor (relies on air cooling)	Fair (can use planes as heatsinks)	Excellent (large surface area for heat dissipation)
Assembly Consistency	Low (manual routing, variable lengths)	High (automated manufacturing)	Very High (pre-fabricated, fixed geometry)
Suitability for High di/dt	Poor	Limited	Excellent

Key Takeaways and Best Practices Checklist

To ensure robust and reliable IGBT performance, engineers must proactively manage parasitic inductance. For additional information on gate control strategies that complement a good physical layout, see our guide on robust gate drive design.

• ✅ Prioritize Low ESL/ESR Capacitors: Select DC link film capacitors specifically designed for low parasitic inductance and resistance.
• ✅ Minimize the Commutation Loop: This is the most critical rule. Place support capacitors as physically close to the IGBT power terminals as possible.
• ✅ Use a Laminated Busbar: For high-power, high-frequency applications, a laminated busbar is the most effective way to minimize interconnect inductance.
• ✅ Optimize PCB Layout: If using a PCB, employ wide, overlapping power planes on adjacent layers to mimic the effect of a busbar.
• ✅ Analyze the Entire System: Remember that total loop inductance is the sum of all parts: capacitor ESL, busbar/PCB inductance, and the IGBT module’s internal inductance.
• ✅ Consider a Snubber Circuit: In some cases where layout inductance cannot be sufficiently minimized, a carefully designed snubber circuit may be necessary to absorb transient energy, though this adds complexity and losses.

Conclusion: From Theory to Reliable Hardware

The battle against IGBT turn-off voltage spikes is won or lost in the design of the physical layout. While the characteristics of the DC link capacitor, specifically its ESL and ESR, are important contributors, they are part of a larger system. The parasitic inductance of the entire commutation loop is the true enemy. By understanding the V = L * (di/dt) relationship and implementing a low-inductance design strategy using either a laminated busbar or an optimized PCB layout, engineers can effectively tame these destructive voltage spikes. This meticulous attention to physical design is no longer a secondary consideration—it is a fundamental requirement for building efficient, reliable, and high-performance power conversion systems with modern high-speed IGBTs.