#74LS112 MIT 74LS112 New Dual JK Negative-Edge-triggered Flip-Flops Cum Serena Et Preset 16-SOIC 0 ad 70, 74LS112 imagines, 74LS112 pretium, #74LS112 elit.
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Email: sales@shunlongwei.com
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Email: sales@shunlongwei.com
https://www.slw-ele.com/74ls112.html
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Manufacturer Pars Number: SN74LS112ADR
Brand Name: Texas Instrumenta
Rohs Code: Sic
Vita parte CIRCUMITUS Code: Active
Ihs Manufacturer: TEXAS INSTRUMENTIS INC
Pars Package Code: SOIC
Sarcina Description: SOP, SOP16,.25
Pin Count: V
ECCN Code: EAR99
HTS Code: 8542.39.00.01
Manufacturer: Texas Instrumenta
Risk Rank: 1.07
Familia: LS
JESD-30 Codex: R-PDSO-G16
JESD-609 Codex: e4
Longitudo: CXCV mm
Load Capacitance (CL): 15 pF
logicae IC Type: JK FLIP-FLOP
max Frequency
Dual JK Negative-Edge-triggered Flip-Flops Cum Serena et consectetur XVI-SOIC 16 usque ad LXX
Brand Name: Texas Instrumenta
Rohs Code: Sic
Vita parte CIRCUMITUS Code: Active
Ihs Manufacturer: TEXAS INSTRUMENTIS INC
Pars Package Code: SOIC
Sarcina Description: SOP, SOP16,.25
Pin Count: V
ECCN Code: EAR99
HTS Code: 8542.39.00.01
Manufacturer: Texas Instrumenta
Risk Rank: 1.07
Familia: LS
JESD-30 Codex: R-PDSO-G16
JESD-609 Codex: e4
Longitudo: CXCV mm
Load Capacitance (CL): 15 pF
logicae IC Type: JK FLIP-FLOP
max Frequency
Dual JK Negative-Edge-triggered Flip-Flops Cum Serena et consectetur XVI-SOIC 16 usque ad LXX