Mastering IGBT Paralleling: A Practical Guide to Current Sharing for Discrete Devices (TO-247)

The “Why” Behind Paralleling: The Need for Higher Current in Modern Power Electronics

In the pursuit of higher power density and system efficiency, power electronics designers frequently face a common challenge: the need for current handling capability that exceeds what a single semiconductor device can provide. While high-power IGBT modules offer a straightforward solution, they often come with a higher price tag and less design flexibility. This is where the strategy of paralleling discrete IGBTs, such as those in the ubiquitous TO-247 package, becomes an attractive and cost-effective alternative. This approach is widely used in applications like solar inverters, welding power supplies, and uninterruptible power supplies (UPS).

However, connecting IGBTs in parallel is not as simple as tying their collectors, emitters, and gates together. The core challenge lies in ensuring that each device carries an equal share of the total current, both during static (on-state) and dynamic (switching) conditions. Any significant imbalance can lead to a cascade of problems, including localized overheating, premature device aging, and catastrophic failure of the entire power stage. Achieving robust and reliable current sharing is a matter of meticulous design, rooted in a deep understanding of IGBT characteristics and circuit layout principles.

The Physics of Imbalance: Key Parameters Affecting Current Sharing

Perfect current sharing is a theoretical ideal. In reality, manufacturing tolerances and operational physics create inherent imbalances. The success of a parallel design depends on mitigating the effects of these key parameter variations.

Vce(sat) and its Temperature Coefficient

The collector-emitter saturation voltage, Vce(sat), is the voltage drop across the IGBT when it is fully turned on. It is a primary determinant of conduction losses. Even within the same manufacturing batch, individual IGBTs will have slightly different Vce(sat) values. The device with the lowest Vce(sat) will naturally try to conduct more current.

The situation is further complicated by the temperature coefficient of Vce(sat).

• Negative Temperature Coefficient (NTC): At lower current densities, Vce(sat) tends to decrease as the junction temperature (Tj) rises. If one IGBT carries more current, it heats up, its Vce(sat) drops further, causing it to draw even more current. This creates a positive feedback loop that can lead to thermal runaway and device destruction.
• Positive Temperature Coefficient (PTC): Fortunately, at higher current densities typical for rated operation, modern IGBTs exhibit a PTC. In this case, as the hotter device’s Tj increases, its Vce(sat) also increases. This rising voltage drop naturally pushes current towards the cooler, parallel devices, creating a self-balancing effect. When paralleling, it is crucial to operate the IGBTs in their PTC region to ensure stable static current sharing.

Gate Threshold Voltage (Vge(th)) Mismatch

The gate threshold voltage, Vge(th), is the minimum gate-emitter voltage required to start turning the IGBT on. Variations in Vge(th) among parallel devices lead to differences in turn-on and turn-off timing. The IGBT with the lower Vge(th) will turn on first and turn off last. During these brief moments, it will carry the entire load current, leading to massive switching loss spikes and potentially exceeding its Safe Operating Area (SOA). This dynamic imbalance is often more destructive than static imbalance.

Parasitic Inductance in Gate and Power Loops

In high-frequency switching applications, even a few millimeters of difference in PCB trace length can introduce significant parasitic inductance.

• Gate Loop Inductance: Asymmetry in the gate drive loop (from the driver IC to the IGBT gate and back) causes different turn-on/turn-off speeds (di/dt). The device with lower gate loop inductance will switch faster, taking on a disproportionate share of the current during the transient. This can also lead to gate voltage ringing and potential oscillations.
• Power Loop Inductance: Mismatched inductance in the main power path (DC bus to collector, emitter back to DC bus) creates unequal voltage drops during switching (V = L * di/dt). The path with lower inductance will experience a higher rate of current change, resulting in a current spike in that specific IGBT.

Practical Design Strategies for Symmetrical Current Distribution

Mitigating the inherent imbalances requires a holistic approach that combines careful component selection, symmetrical layout, and robust gate drive design. For a detailed exploration of this topic, Infineon’s application note on demystifying the paralleling of IGBT modules provides excellent insights that are also applicable to discrete devices.

Symmetrical PCB Layout: The Foundation of Success

The physical layout of the printed circuit board is arguably the single most important factor in achieving good current sharing. The goal is to make the electrical and thermal environment for each parallel IGBT as identical as possible.

• Star Connections (Kelvin Principle): Avoid daisy-chaining connections. Both the high-current power paths (DC+ and DC-) and the low-current gate drive signals should originate from a central “star” point and branch out to each IGBT. This ensures that the path length, and thus the parasitic inductance and resistance, is nearly identical for every device.
• Physical Placement: Arrange the IGBTs symmetrically on the PCB and heatsink. A “domino” or linear arrangement can create imbalances, where the devices at the ends of the line have different thermal and inductive paths than those in the middle. A circular or rectangular grouping around a central connection point is often preferred.
• Decoupling Capacitors: Place high-frequency decoupling capacitors as close as possible to the collector-emitter pins of each IGBT, not just at a central point. This provides a low-inductance path for switching currents, reducing voltage overshoot and improving dynamic performance for all devices.

Gate Drive Circuit Design for Parallel Operation

A well-designed gate drive is critical for controlling dynamic current sharing.

• Individual Gate Resistors: Never use a single, shared gate resistor. Each IGBT must have its own dedicated gate resistor (Rg) placed as close as possible to the gate pin. This helps to dampen parasitic oscillations between parallel devices and allows for fine-tuning of the switching speed for each IGBT. The resistor values should be identical.
• Ferrite Beads: Placing a small ferrite bead in series with the gate resistor can help suppress very high-frequency oscillations that can occur due to interactions between the gate capacitance and loop inductance.
• Low-Impedance Driver: The gate driver IC must have a very low output impedance and high peak current capability to charge and discharge the gate capacitances of all parallel IGBTs simultaneously and swiftly. A weak driver will result in slow, sloppy switching and exacerbate timing mismatches.
• Kelvin Emitter Connection: For optimal performance, use devices with a Kelvin emitter pin (available in packages like TO-247-4). This provides a separate, clean return path for the gate driver current, isolating it from the high and noisy power current flowing through the main emitter. This prevents feedback that can corrupt the gate drive signal.

Thermal Management: The Unsung Hero of Stability

Electrical symmetry is useless without thermal symmetry. Because Vce(sat) is temperature-dependent, ensuring all IGBTs operate at the same temperature is crucial for static current balancing.

• Common Heatsink: Always mount all paralleled IGBTs on a single, continuous heatsink. This provides a tight thermal coupling, allowing heat to spread and average out the temperatures across the devices.
• Uniform Mounting: Use a calibrated torque wrench to ensure uniform clamping pressure for all devices. Inconsistent pressure leads to variations in thermal resistance (Rth), causing some devices to run hotter than others.
• High-Quality TIM: Apply a thin, even layer of a high-performance Thermal Interface Material (TIM) between each IGBT and the heatsink to minimize contact thermal resistance.

Analyzing a Common Failure Scenario: A Case Study

Problem: A team was developing a 15kW motor drive using four TO-247 IGBTs in parallel per switch position. During full-load testing, the same device (IGBT #4) failed repeatedly after only a few minutes of operation.

Investigation & Solution: An initial review showed the devices were from the same batch. However, a close inspection of the PCB revealed a daisy-chain layout for the power connections. IGBT #1 was closest to the DC bus capacitor, while IGBT #4 was at the far end of the chain. This meant IGBT #4 had the highest parasitic inductance in its power loop. Oscilloscope measurements confirmed that IGBT #4 experienced significantly higher voltage overshoot and turn-on current spikes. The thermal camera also showed its case temperature was 15°C higher than the others just before failure, indicating severe current hogging. The solution was a complete PCB redesign. The new layout implemented a central star-point for the DC bus and a symmetrical “H” pattern for the gate drive traces, ensuring equal path lengths for all four devices.

Result: The redesigned board was tested under the same full-load conditions. The current was measured on each IGBT’s emitter, showing a distribution imbalance of less than 4%, compared to over 25% on the original design. The temperatures were uniform across all four devices, and the system passed all long-duration stress tests without failure.

Key Takeaways: A Checklist for Robust Parallel IGBT Design

To ensure a successful and reliable parallel IGBT design, follow this checklist during your development process.

Design Area	Key Action / Consideration	Rationale
Device Selection	Select IGBTs from the same manufacturing batch. If possible, sort them for closely matched Vce(sat) and Vge(th).	Minimizes initial parameter deviation, providing a better starting point for balancing.
PCB Layout	Implement a fully symmetrical layout using star-point connections for both power and gate drive paths.	Equalizes parasitic inductance and resistance, which is the most critical factor for dynamic current sharing.
Gate Drive	Use a dedicated, identical gate resistor for each IGBT. Employ a low-impedance driver and Kelvin emitter connections if available.	Ensures controlled, simultaneous switching and prevents parasitic oscillations.
Thermal Design	Mount all devices on a common, high-capacity heatsink with uniform pressure and high-quality TIM.	Promotes thermal coupling and temperature uniformity, which is essential for stable static current sharing.
Validation	Measure the current in each branch and the temperature of each device under various load conditions.	Verifies that the design achieves the desired current and thermal balance in real-world operation.

Conclusion: From Theory to Reliable High-Power Designs

Paralleling discrete IGBTs is a powerful technique for building high-current, cost-effective power stages. However, success is not accidental; it is the result of a disciplined engineering approach. By focusing on symmetry in every aspect of the design—from the electrical layout to the thermal management—engineers can overcome the inherent challenges of device mismatches. A design that prioritizes symmetrical layouts, robust individual gate driving, and tight thermal coupling will transform a collection of individual components into a single, reliable, high-performance power switch capable of meeting the demands of modern power electronics.