The hardware, called ‘VISC’, is an accelerated RISC-V core that “optimises complex mathematical algorithms for parallel execution in its reconfiguration hardware engine”, according to Red, which claims: “The VISC ISA [instruction set] enables developers to describe complex algorithms in just a fraction of the code size it would take with the standard RISC-V instruction set, […]
RED Semiconductor (“RED”) announces VISC, an algorithmic microprocessor ISA and hardware design that extends the capabilities of RISC-V for Edge AI, autonomy and cryptography. VISC is an accelerated RISC-V microprocessor core, which optimises complex mathematical algorithms for parallel execution in its reconfiguration hardware engine. The performance boost delivered by VISC, compared with standard RISC-V, is […]
The S32 CoreRide platform brings together NXP’s S32 compute, networking, system power management and ready-to-deploy software from the company’s extensive software partner ecosystem. The company is also unveiling its first S32 CoreRide solution for central compute based on NXP’s new S32N family of vehicle super-integration processors. It offers safe and scalable combinations of real-time and […]
Chiplet testing begins with performance simulations during the design process. Compared with monolithic devices, heterogeneous chiplets require more complex testing, including known good die (KGD) testing, final test, and system level test. Success also depends on the implementation of design for test (DfT) based on several IEEE standards. Chiplet designers need high-speed tools that can […]
March 28, 2024 — Renesas Electronics Corporation recently announced the industry’s first general-purpose 32-bit RISC-V-based microcontrollers (MCUs) built with an internally developed CPU core. While many MCU providers have recently joined investment alliances to advance the development of RISC-V products, Renesas has already designed and tested a new RISC-V core independently, which is now implemented in […]
Generative artificial intelligence (AI) requires rapid and continuous movement of large amounts of data. In a growing number of instances, electrical input/output (I/O) connections between the ICs in chiplets are becoming a bottleneck to higher performance. Key electrical I/O performance barriers include power efficiency, bandwidth, and latency. This FAQ looks at the anticipated benefits of […]
Annealing processors are designed specifically for addressing combinatorial optimisation problems, where the task is to find the best solution from a finite set of possibilities. With CMOS ICs it is necessary for the components of annealing processors to be fully “coupled.” However, the complexity of this coupling directly affects the scalability of the processors. Led […]
“Bluespec’s RISC-V processors now integrate into the Achronix 2D network-on-chip architecture, simplifying integration and enabling engineers to add scalable processing to their designs,” according to Achronix. “The network allows multiple instances of the RISC-V core to be added, and relocated to different areas of the FPGA fabric while maintaining performance.” Developers, it went on to […]
indie Semiconductor, Inc., an Autotech solutions innovator, today announced a strategic investment in Expedera Inc, a leading provider of scalable Neural Processing Unit (NPU) semiconductor intellectual property (IP). The partnership will deliver customised artificial intelligence (AI) enabled processing capabilities for sensing solutions targeting Advanced Driver Assistance Systems (ADAS) and includes a commercial agreement to integrate […]