Loss Modeling and Efficiency Prediction for SiC MOSFETs in Solid-State Transformer High-Frequency Stages

The modernization of our electrical grid hinges on the adoption of smarter, more flexible, and highly efficient power conversion technologies. At the forefront of this evolution is the Solid-State Transformer (SST), a power electronics-based transformer poised to replace traditional line-frequency magnetic transformers in applications ranging from renewable energy integration and EV charging infrastructure to microgrids. A critical component within the SST is the high-frequency isolated DC-DC stage, where achieving high efficiency at high switching frequencies is paramount. This is where Silicon Carbide (SiC) MOSFETs have emerged as the undisputed enabling technology, but harnessing their full potential requires a deep, quantitative understanding of their loss mechanisms.

For design engineers, simply selecting a SiC MOSFET based on its R_DS(on) is insufficient. Accurately predicting the thermal performance and overall efficiency of an SST’s DC-DC stage requires a robust loss model. This article provides a practical, engineering-focused guide to modeling SiC MOSFET losses, predicting converter efficiency, and understanding the critical trade-offs in high-frequency SST applications.

Deconstructing SiC MOSFET Losses: A Foundational Approach

The total power loss in a SiC MOSFET is the sum of several components, each becoming more significant under different operating conditions. A precise model must account for them all, especially their dependency on junction temperature, which is a critical factor in real-world applications.

Conduction Losses (P_cond)

Conduction loss occurs when the MOSFET is in its ‘on’ state, acting like a resistor. It is calculated using the on-state resistance (R_DS(on)) and the RMS current (I_rms) flowing through the device. However, R_DS(on) is not a fixed value; it increases significantly with junction temperature. A common mistake is to use the 25°C datasheet value, which can lead to a gross underestimation of losses at operating temperature.

P_cond = I_rms² × R_DS(on)(T_j)

Where T_j is the operational junction temperature. For accurate modeling, it’s essential to use the R_DS(on) vs. Temperature curve from the device datasheet.

Switching Losses (P_sw)

Switching losses are the dominant loss factor in high-frequency converters like those in SSTs. They occur during the brief transitions between the on and off states. These losses are directly proportional to the switching frequency (f_sw).

P_sw = (E_on + E_off) × f_sw

Here, E_on (turn-on energy) and E_off (turn-off energy) are not constants. They depend on the drain current (I_D), DC bus voltage (V_DS), and, crucially, the junction temperature. Modern datasheets provide 3D graphs showing these dependencies, which are vital for an accurate model. SiC MOSFETs exhibit dramatically lower switching losses compared to Si IGBTs, primarily due to the absence of “tail current” during turn-off, enabling efficient operation at frequencies well over 100 kHz.

Other Significant Loss Mechanisms

• Body Diode Losses: In topologies like the Dual Active Bridge (DAB), the body diode conducts during the dead time. SiC MOSFET body diodes have a higher forward voltage drop compared to their channel, making this a significant source of loss. This includes both conduction loss during the dead time and reverse recovery loss (Q_rr). While Q_rr in SiC is much smaller than in Si, it is not zero and contributes to the turn-on loss of the complementary device.
• Output Capacitance Loss (P_oss): The energy stored in the parasitic output capacitance (C_oss) is dissipated as heat during each turn-on event, unless zero-voltage switching (ZVS) is achieved. In hard-switched applications, this can be calculated as: P_oss = ½ × C_oss × V_DS² × f_sw. Achieving ZVS is a key design goal in high-frequency converters to minimize this loss.
• Gate Drive Loss (P_gate): This is the power required to charge and discharge the gate capacitance (Q_g) at each switching cycle. It is calculated as: P_gate = Q_g × V_GS × f_sw. While typically smaller than conduction or switching losses, it should not be neglected in high-frequency designs.

Building an Accurate Loss Model: From Datasheet to Reality

Developing a practical loss model involves a systematic process of extracting data and applying it to the converter’s operating conditions. An accurate model is not just an academic exercise; it’s a critical tool for thermal design and reliability analysis, directly impacting everything from heatsink selection to system lifetime. For a deeper dive into the principles of modeling, resources like our guide on accurate loss modeling in simulation software provide a strong foundation.

Step 1: Gather Temperature-Dependent Parameters

The foundation of any good model is quality data. Go through the SiC MOSFET datasheet and extract the following curves, not just single-point values:

• R_DS(on) vs. T_j
• E_on and E_off vs. I_D at various T_j
• Body diode forward voltage (V_SD) vs. I_F and T_j
• Gate charge (Q_g) vs. V_GS
• Parasitic capacitances (C_iss, C_oss, C_rss) vs. V_DS

Step 2: Model Losses Across the Load Profile

Losses are not constant. They change with the load current. A comprehensive model should calculate losses at various operating points (e.g., 10%, 25%, 50%, 75%, 100% load). This involves calculating the device current for each point and using the extracted datasheet curves to find the corresponding R_DS(on) and switching energies. An iterative approach is often needed, where an initial T_j is assumed, losses are calculated, and the resulting temperature rise is used to update T_j until the value converges.

Step 3: Factor in System-Level Influences

A device-level model is only part of the story. Parasitic inductance in the PCB layout (L_stray) can cause voltage overshoot and ringing, increasing turn-off losses. The gate driver design, including the choice of external gate resistor (R_g), directly impacts switching speed and, therefore, the balance between E_on/E_off and EMI performance.

SiC MOSFET vs. Si IGBT in SSTs: A Comparative Loss Analysis

To understand why SiC is the preferred choice for the high-frequency stage in SSTs, a direct comparison with the best-in-class high-speed Silicon IGBTs is illustrative. While IGBTs are workhorses in many power applications, their limitations become clear as switching frequencies increase. The battle between these technologies is a key consideration in modern power design, much like the SiC vs. IGBT debate in EV chargers.

Parameter	SiC MOSFET	High-Speed Si IGBT
Typical f_sw in SST	100 kHz – 500 kHz+	20 kHz – 50 kHz
Switching Losses	Very Low (no tail current)	High (due to tail current), limits frequency
Conduction Losses	Resistive (I²R), efficient at light loads. Increases with temperature.	V_CE(sat) + Resistive, less efficient at light loads due to knee voltage.
Body Diode Performance	Fast but high V_F. Low Q_rr. Synchronous rectification is often used to bypass it.	Co-packed diode optimized for speed, but Q_rr is still significant.
Thermal Performance	Higher intrinsic thermal conductivity and max T_j (175-200°C), simplifying thermal resistance management.	Lower max T_j (typically 150-175°C), requires larger cooling systems.
System-Level Impact	Significantly smaller magnetics, capacitors, and heatsinks. Higher power density and efficiency (98%+ achievable).	Larger, heavier, and more costly passive components due to lower f_sw.

From Loss Model to Efficiency Prediction: A Practical Workflow

With a robust loss model, you can confidently predict the converter’s efficiency curve, a critical deliverable for any power electronics project.

Case Study: 50kW Dual Active Bridge (DAB) Converter

Problem: Design a 50kW, 100 kHz DAB isolation stage for an SST, connecting an 800V bus to a 400V bus, with a target peak efficiency >98.5%.

Solution Workflow:

1. Device Selection: Based on voltage/current requirements, select a few candidate 1200V SiC MOSFETs.
2. Loss Calculation: Using the model described above, calculate the total per-device loss (P_total = P_cond + P_sw + P_diode + P_oss) for each candidate across the entire load range (e.g., 5kW to 50kW). Remember to use temperature-corrected values. Many studies show that fully SiC-based DABs can reduce total device loss by 40% or more compared to Si-IGBT solutions.
3. Thermal Analysis: Use the calculated P_total and the module’s thermal resistance (R_th,j-c) to calculate the junction temperature rise (ΔT_j = P_total × R_th,j-c). Ensure the predicted T_j remains well within the device’s Safe Operating Area (SOA).
4. Efficiency Prediction: Calculate the total converter loss (P_total_conv = Number of devices × P_total) and predict the efficiency at each load point:
   
   η (%) = [P_out / (P_out + P_total_conv)] × 100

The resulting data can be plotted to generate an efficiency curve (Efficiency vs. Output Power), which is the ultimate measure of the design’s success.

Validating the Model: The Indispensable Double-Pulse Test

While simulations and analytical models are powerful, they must be anchored in reality. The double-pulse test is the industry-standard method for experimentally measuring the switching energies (E_on, E_off) and reverse recovery characteristics of a device under controlled conditions. The results from this test can be used to validate or fine-tune the parameters used in your loss model, ensuring your predictions are not just theoretical but are backed by empirical data.

Key Takeaways for Engineers and System Designers

• Temperature is Everything: Always use temperature-dependent parameters for R_DS(on) and switching energies. Room-temperature values are misleading.
• Switching Loss Dominates: In high-frequency SST applications, switching losses are the primary challenge. Your ability to model them accurately will define your thermal design.
• ZVS is the Goal: Strive for Zero-Voltage Switching to eliminate output capacitance losses and significantly boost efficiency, especially at higher bus voltages.
• Don’t Neglect the Passives: Your choice of SiC device directly impacts the size, cost, and loss of the transformer and filter components. The entire ecosystem benefits from higher frequency.

Ultimately, the move toward SiC-based Solid-State Transformers is driven by the pursuit of higher efficiency and power density. By moving beyond simplified calculations and embracing a detailed, temperature-aware loss modeling methodology, engineers can unlock the full performance of these advanced semiconductors, designing converters that are not only smaller and lighter but also significantly more efficient. This careful analysis is the key to building the next generation of reliable, high-performance power grids. For your next SST design, start with a robust model and select components from trusted manufacturers like Infineon or Fuji Electric to ensure your theoretical gains translate into real-world success.