Marvell unveils new silicon platform based on TSMC’s 3nm process technology
Marvell has unveiled an advanced silicon platform based on TSMC’s 3nm process technology, offering better power, performance, and area for the data infrastructure industry.
Marvell will have IP cores on upcoming TSMC 3nm silicon releases, which means that customers will be able to take advantage of one of the world’s most advanced Semiconductor technologies in conjunction with other proven silicon components to build more complex, system-optimised solutions for the cloud data centre, 5G carrier, automotive and enterprise markets.
Marvell will be the first company to introduce a comprehensive standards-based silicon platform for multi-chip solutions that leverages the latest process technology, advanced die-to-die interface IP, and TSMC’s advanced 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging technology.
in addition to the extensive IP portfolio currently offered Marvell, this new 3nm multi-chip platform includes two complementary advanced die-to-die interfaces.
The first is a flexible extra short reach (XSR) interface for connecting multiple die on a package substrate for applications, like co-packaged optics (CPO) for cloud data centres.
To address the growing needs for cloud-optimised silicon solutions, Marvell is also developing an ultra-low power and low-latency parallel die-to-die interface with the highest bandwidth density in the industry.
Compatible with emerging Open Compute Project (OCP) standards, the new parallel interface enables high-performance chiplet solutions by connecting multiple silicon devices on an interposer. Both interfaces are also available in 5nm to enable multi-node solutions.
The new platform also incorporates TSMC’s advanced CoWoS packaging technology, empowering continued data infrastructure performance scaling. Marvell’s collaboration with TSMC on CoWoS will allow customers to build high-performance solutions for the most demanding cloud data centre applications.