The toolchain supports all 32bit Andes V5 Risc-V cores, including N22, N25F, D25F, A25, A27, N45, D45 and A45. Risc-V Packed SIMD/DSP extension specification (RVP draft) and the corresponding intrinsic functions as well as Andes DSP libraries are supported.
“AndeStar V5 offers compatibility to Risc-V technology by supporting its standard instructions,” said Andes CTO Charlie Su. “In addition, it incorporates Andes-extended features such as Performance extension and CoDense extension.”
Embedded Workbench is a C/C++ compiler and debugger toolchain, in this case for Risc-V. It includes C-STAT for static code analysis. “C-STAT proves code alignment with industry standards like MISRA C:2012, MISRA C++:2008 and MISRA C:2004, and also detects defects, bugs, and security vulnerabilities as defined by CERT C and the Common Weakness Enumeration,” according to IAR.
For safety-critical applications, Embedded Workbench for Risc-V is available in a functional safety edition certified by TÜV SÜD according to IEC 61508, ISO 26262, IEC 62304, EN 50128, EN 50657, IEC 60730, ISO 13849, IEC 62061, IEC 61511 and ISO 25119.